libfpga-myhdl

beta

The same building blocks in MyHDL, hardware described in Python.

✓ Claimed by @libfpga. This listing is owner-controlled via a libfpga.yaml manifest in the repository.

LicenseMIT
Languagesmyhdl, python
Interfacesuart, spi
Targetsdevice-agnostic
Categorylibrary

Source on GitHub → Docs / homepage

Verification

Signals earned by running the open toolchain. This is the registry's whole point: know it works before you clone it.

Lints clean ✓ Testbench passes Synthesizes Formally proven ✓ Converts to RTL
Runs our toolchain against your declared sources.

About

The Python companion to libfpga: verified building blocks in MyHDL that simulate in pure Python, convert to Verilog and VHDL, and are co-simulated so the generated RTL provably matches the model.

cdcfifouartspilfsrmacarbiterpythoncosimulation