libfpga-myhdl

beta

The same building blocks in MyHDL, hardware described in Python.

Install with lfpga lfpga add libfpga-myhdl

✓ Claimed by @libfpga. This listing is owner-controlled via a libfpga.yaml manifest in the repository.

LicenseMIT
Languagesmyhdl, python
Interfacesuart, spi
Targetsdevice-agnostic
Categorylibrary

Source on GitHub → Docs / homepage

Verification

Signals earned by running the open toolchain against the public source. This is the registry's whole point: know it works before you clone it.

✓ Lints clean ✓ Testbench passes ✓ Synthesizes Formally proven Converts to RTL

Last checked 2026-07-05 by the LibFPGA toolchain.

Runs our toolchain against your declared sources.
Show it off in your README: lfpga registry status [![lfpga](https://libfpga.com/cores/libfpga-myhdl/badge.svg)](https://libfpga.com/cores/libfpga-myhdl)

About

The Python companion to libfpga: verified building blocks in MyHDL that simulate in pure Python, convert to Verilog and VHDL, and are co-simulated so the generated RTL provably matches the model.

cdcfifouartspilfsrmacarbiterpythoncosimulation

Related cores

libfpga ✓ Verified reusable Verilog building blocks for FPGA designs. library fpga-neuron ✓ An educational neural network on an FPGA, from a single neuron to an XOR net. example verilog-ethernet ✓ Ethernet MAC and UDP/IP stack components in Verilog. networking · ★ 3,018 FPGA-USB-Device ✓ An FPGA-based USB 1.1 full-speed device (no PHY chip). usb · ★ 906 verilog-uart ✓ A simple, widely-used Verilog UART with an AXI-Stream interface. interconnect · ★ 574 core_usb_cdc ✓ A basic USB-CDC (serial) device core in Verilog. usb · ★ 91

Tools for this

FIFO Depth Calculator Minimum FIFO depth for a write burst crossing into a slower reader. LFSR Generator Maximal-length LFSRs (2-64 bits) with ready-to-use Verilog and VHDL. UART Baud Rate Calculator Clock divisor, real baud rate and error % for any clock/baud pair. CDC Synchronizer Generator 2-flop sync, pulse sync, reset sync and debouncer - with constraints.