Clock divider (do it with an enable)

When to use it

You want part of your design to tick slower, once every N clocks. The right way on an FPGA is a clock enable: keep one fast clock everywhere and gate the logic with a one-cycle tick pulse. Do not build a divided net and use it as a clock, that skips the clock tree and invites skew and hold violations.

How it works

A counter rolls over every N clocks and pulses tick high for one cycle. Anywhere you'd want the slow clock, write if (tick) ... instead. If you genuinely need a slower square wave (say, to drive an LED), toggle a flop on tick, that's slow here.

Gotchas

• Use tick as an enable, not as a clock. Feeding slow into another block's clock port is the classic beginner mistake.
• For non-integer rates, accumulate a fraction each clock and tick on overflow, see the verified lfpga_clkdiv_frac.