Skid buffer

When to use it

On a valid/ready (AXI-stream) bus, you often want to add a register stage to break a long timing path. But a naive register stalls a cycle whenever the downstream isn't ready, and worse, wiring ready straight through defeats the point. A skid buffer registers both directions yet still moves one beat per cycle.

How it works

It keeps one extra holding ("skid") register. While the output is stalled and a new beat arrives, that beat skids into the holding register instead of forcing the upstream to stop on the same cycle. When the output frees up, the skidded beat moves out first. So upstream only sees backpressure one cycle late, which is exactly enough to register the ready signal.

Gotchas

• The point is a registered valid, ready and data, no combinational path straight through. That's what lets it close timing.
• It adds one cycle of latency and holds up to two beats in flight. Account for that in any credit or flow-control logic upstream.