SPI master

When to use it

SPI is the go-to for talking to sensors, ADCs, flash and displays. The master drives a clock (sclk) and chip-select (cs_n) and shifts data out on mosi while reading miso back, full duplex. This is mode 0 (CPOL=0, CPHA=0): sample on the rising edge, change on the falling edge.

How it works

Lower cs_n, then for each of 8 bits toggle sclk: present the next mosi bit while the clock is low, and sample miso on the rising edge. After 8 bits, raise cs_n. rx_data holds whatever the peripheral shifted back.

Gotchas

• Match the peripheral's mode (CPOL/CPHA). Get it wrong and every bit is off by half a clock.
• Keep cs_n low for the whole transfer; many devices reset their shift logic when it rises. The verified lfpga_spi_master parameterises the mode and bit count.