FPGA Boards for AI: a 2026 Field Guide

We have made the case twice already: that an FPGA is shaped like a neural network, and that when you quantize all the way to a single bit, a look-up table stops approximating a neuron and becomes one. Those posts answer why. This one answers the question that arrives the moment you are convinced: which board do I actually buy?

It is a deeper question than it looks, because the FPGA-for-AI market is not one market. It runs from chips that classify a wake-word on a coin cell at a few milliwatts, all the way to 250-watt datacenter cards streaming inference at line rate. Buy from the wrong end of that range and you will either starve your model or heat your desk for nothing. So this is a field guide: the tiers, the boards that define each one, the software that actually makes them run, and an honest read on where FPGAs beat a GPU and where they do not.

One rule before we climb, and it is the rule most buying guides bury: the software stack matters as much as the silicon. A board with a mature compiler and a model zoo gets you to a working demo in an afternoon; the same gates with no toolchain cost you a month.

Tier 1: milliwatt, always-on edge

At the bottom of the ladder are the parts built to stay awake for years on a battery, watching for one thing. This is the home of always-on inference: keyword spotting, human-presence detection, gesture and vibration classification, the tireless front end that decides when to wake something bigger.

Lattice owns the popular imagination here. The venerable iCE40 UltraPlus (the UP5K, with 5,280 logic cells, eight DSP blocks and a full megabit of on-chip SRAM) exists precisely so a tiny convolutional net can live in the fabric while the host processor sleeps. Lattice quotes standby currents in the low hundreds of microamps, and one of their reference designs claims person detection at around 7 mW (a vendor reference figure rather than an independent measurement, but the order of magnitude is the point). Step up to the Nexus platform (28 nm) and the CrossLink-NX and CertusPro-NX families add MIPI camera lanes and enough logic for real embedded-vision models, still at a fraction of a typical SoC's power. All of it runs on Lattice's sensAI stack, which is actively maintained (sensAI 8.0 landed at the end of 2025) and ships CNN and binarized-neural-network accelerator IP plus a compiler that quantizes a trained Keras or TensorFlow Lite model onto it.

Microchip attacks the same edge from a different angle with PolarFire, a 28 nm non-volatile FPGA. Because the configuration lives in flash, the chip is instant-on, single-chip, and draws famously low static power, which matters when your device is idle 99% of the time. PolarFire SoC hardens a five-core RISC-V complex (four Linux-capable application cores plus a real-time monitor core) next to the fabric, so one chip runs your OS, your control loop, and your accelerator. That accelerator is Microchip's VectorBlox: a matrix-processor overlay plus an SDK that deploys quantized (TensorFlow Lite INT8) CNNs as software binaries you can swap at runtime without re-synthesizing the FPGA, a genuinely useful property for a field-updated product.

Who it is for: battery-powered products, sensors, and always-on wake stages where a watt is a luxury and the model is small. The dev kits are cheap, the Lattice presence-detection boards sit around $130 to $250, and a Microchip Icicle kit is about $420.

Tier 2: the edge dev-kit sweet spot

This is where most people should start, and where a great many real embedded-AI products actually ship. The parts are AMD Zynq UltraScale+ MPSoC devices: an FPGA fabric welded to a quad-core Arm processor, with enough DSP and block RAM to run serious quantized CNNs at tens of frames per second inside a 5-to-20-watt envelope.

The standout is the AMD Kria line, because it is the friendliest on-ramp in the whole ecosystem and one of the few products with an honest public price. The KV260 Vision AI starter kit is $249, boots from an SD card, and runs pre-built accelerated vision apps from AMD's Kria App Store on day one; the KR260 Robotics kit ($349) adds native ROS 2. Both carry the K26 system-on-module (a custom Zynq UltraScale+ with roughly 1.4 INT8 TOPS on tap) that you can later design straight into a product. Around them sit the classic eval boards, the ZCU104 and ZCU106, and Avnet's pocket-sized Ultra96-V2.

The engine that makes all of this go is AMD's Vitis AI and its DPU (Deep-learning Processing Unit), a configurable INT8 matrix engine that you instantiate in the fabric as a soft overlay. You quantize a PyTorch or TensorFlow model, compile it to the DPU's instruction set, and run it, no HDL required. For pure learning, the Zynq-7000-based PYNQ-Z2 (about $199) lets you drive the fabric from Python in a Jupyter notebook, though be warned that the modern DPU flow really wants an UltraScale+ part and the PYNQ DPU overlay project was archived in 2025. Treat the little Zynq-7020 boards as a place to learn PYNQ and HLS, not as a DPU inference target.

Who it is for: anyone learning FPGA AI, prototyping a vision or robotics product, or shipping an embedded system that needs a few TOPS with a Linux stack right next door. If you buy one board from this article, make it a KV260.

Tier 3: high-performance embedded (the AI Engine era)

Above the MPSoCs, AMD's Versal architecture changes the game. Versal is an "adaptive SoC" that adds a hardened array of AI Engines, vector processors that live beside the fabric and are tied to it by a hardened network-on-chip. This is no longer "fit a small net in the LUTs"; it is a dedicated ML compute array doing hundreds of INT8 tera-ops.

For embedded work the relevant family is Versal AI Edge. The Gen 1 evaluation board, the VEK280, carries AI-Engine-ML tiles tuned for machine learning (INT8, INT4, BF16). In 2025 AMD shipped Gen 2, and by early 2026 its VEK385 kit reached broad availability: a larger, safety-oriented Arm complex, PCIe Gen5, and AI-Engine-ML v2 tiles that add FP8 and micro-scaling formats, with a vendor peak in the neighborhood of 180 INT8 TOPS. These are not weekend boards (the VEK385 lists around $16,000), but they are what goes into ADAS, medical imaging, radar, and sensor-fusion systems that need a lot of deterministic inference inside a sealed thermal budget.

Who it is for: product teams building high-end embedded AI where latency is a contract and a GPU's power draw and jitter are non-starters. Bring a real budget and a real schedule.

Tier 4: datacenter accelerator cards (and an honest surprise)

At the top sit the PCIe cards, and here the story took a genuinely interesting turn that most guides have not caught up with.

The conventional picture is a rack of FPGA cards doing high-throughput inference, and the parts certainly exist. AMD's Alveo cards (U50, U55C, U250, U280) pair big UltraScale+ fabric with HBM or DDR4; Altera (more on the name shortly) offers Agilex 7, whose M-Series stacks HBM2E for around a terabyte per second of bandwidth, and the older Stratix 10 NX, the first Intel FPGA built for AI, with a peak near 143 INT8 TOPS from its AI Tensor Blocks. Achronix rounds out the "AI-optimized FPGA" trio with the 7 nm Speedster7t and its VectorPath card ($8,495), whose 2,560 Machine-Learning-Processor blocks and 2D network-on-chip give a peak somewhere in the 60-to-86 TOPS range depending on whose slide you read.

Here is the honest surprise, worth knowing before you spend: the turnkey FPGA-datacenter-inference story has quietly retreated. AMD dropped Vitis AI support for the entire legacy UltraScale+ Alveo line at Vitis AI 3.0; its purpose-built Versal inference card, the V70, was discontinued in early 2025; and the current flagship Alveo V80 ($9,495) is explicitly marketed as an HBM compute accelerator, not a drop-in inference product. Achronix's real-world numbers make the same point: an independent overlay measured 36.4 TOPS on a VectorPath card, against a headline peak nearly twice that, a healthy reminder that peak TOPS and delivered TOPS are different animals. And FPGAs have all but vanished from the recent MLPerf Inference rounds, which now read as a GPU contest.

The takeaway is not that FPGAs lost the datacenter; it is that their datacenter win is specialized. Ultra-low-latency finance, network-inline filtering, custom-precision research: yes. "A cheaper GPU for serving models": no, buy a GPU for that.

Who it is for: teams with a specific low-latency or custom-dataflow datacenter problem and the FPGA engineers to build it. If you just want a model served at high throughput on a mature stack, this tier will frustrate you.

The lineup at a glance

Prices are volatile 2026 distributor figures, and every TOPS number except the Achronix "measured" one is a vendor peak. Treat them as a map, not a spec sheet.

Two 2026 headlines that change how you shop

Two industry shifts happened recently enough to reshape the landscape, and knowing them makes you a sharper shopper:

1. Xilinx is gone as a name; the products are AMD now. The 2022 acquisition is fully digested: it is AMD Versal, AMD Kria, AMD Alveo, built in Vivado and Vitis. Older tutorials that say "Xilinx" still apply, but the store, the forums, and the roadmaps are all AMD.
2. Altera is independent again. Intel relaunched the Altera brand in 2024, then sold a controlling 51% stake to Silver Lake in a deal that closed in September 2025. Altera is now a standalone FPGA company (under CEO Raghib Hussain) betting its AI story on the AI Tensor Block woven throughout the Agilex 5 fabric, plus the FPGA AI Suite compiler. In practice the Altera AI flow is FPGA AI Suite with OpenVINO; the old assumption that FPGA AI lives inside mainline oneAPI or the OpenVINO FPGA plugin is out of date, since both were wound down (the OpenVINO FPGA plugin back in 2020).

The part that actually decides your project: the toolchain

You do not deploy a model to a board; you deploy it through a compiler. Choose the compiler first, and let it choose the board.

• Vitis AI + DPU (AMD) is the most turnkey path: quantize, compile, run on a DPU overlay across Kria, Zynq UltraScale+, and Versal. Widest coverage, INT8, the shortest road to a working demo.
• FPGA AI Suite + OpenVINO (Altera) is the mirror-image path for Agilex and Stratix 10: train in TensorFlow or PyTorch, let OpenVINO optimize, and generate right-sized inference IP into Quartus.
• sensAI (Lattice) and VectorBlox (Microchip) own the low-power edge, each with a model zoo and, in VectorBlox's case, runtime-swappable models with no re-synthesis.
• FINN + Brevitas (open source) is the purest "the network becomes the chip" flow: train a binary or low-bit network in Brevitas, and FINN compiles it into a bespoke streaming dataflow accelerator. It is the direct descendant of the XNOR-popcount neuron we built by hand.
• hls4ml (open source) compiles compact models to HLS for the sub-microsecond regime; born at CERN to trigger particle collisions, it is the tool when your latency budget is measured in nanoseconds.

If a board does not appear in the framework you plan to use, that is not a detail. That is the project.

FPGA vs GPU vs ASIC, without the hype

It helps to place FPGAs on the one spectrum that actually explains them:

Move left and you gain flexibility and ease (a CPU runs anything; a GPU adds enormous throughput with a fixed menu of number formats). Move right and you gain efficiency at the cost of freedom (an ASIC or TPU is beautifully efficient and utterly frozen the day it tapes out). FPGAs sit in the productive middle, and they earn their keep on four things:

• Deterministic latency. Inference runs in a fixed count of clock cycles, no scheduler, no cache warm-up, no tail. FPGA neural-net latencies of 100 ns to 10 µs are routine, and they do not vary.
• Custom and mixed precision. Per-layer INT8, INT4, ternary, binary, or a block-float scheme of your own. This is structurally impossible on a fixed-datatype GPU or a Google Edge TPU (which, to be clear, is an ASIC, not an FPGA, and is INT8-only).
• Inline dataflow. The FPGA already sits on the camera lane or the network MAC, so inference becomes one more pipeline stage with no PCIe round trip.
• Reconfigurability. New model, new standard, new bitstream. Microsoft's Project Brainwave famously chose FPGAs over an ASIC for exactly this.

And the honest debits: FPGAs are an inference-and-edge story, not a training story (that is GPU country); a volume ASIC beats them on raw efficiency and unit cost; and the developer experience, hours of synthesis versus a pip install, is still the real tax. That is precisely why the toolchain section came first.

(A note on a persistent myth: FPGAs are the standard prototyping vehicle for AI ASICs before tapeout, and sometimes the permanent choice when flexibility beats efficiency. But do not let anyone tell you the famous inference ASICs "started life as FPGAs". Most, Google's TPU included, were ASICs from day one.)

Start this weekend, board optional

You do not need to spend $249 to begin. The XNOR-popcount neuron from our binary-networks post runs right here in your browser, edit the weights, press Run, and watch a multiply-free neuron fire:

When you are ready for real silicon, the honest first purchase is a Kria KV260: it is affordable, it has the best on-ramp in the business, and Vitis AI will have you running a quantized vision model in an afternoon. Pair it with our fixed-point converter to build quantization intuition, clone the neural micro-kit to watch a trained network become verified Verilog, and browse the board picker when you want to compare what is sitting on your desk. Neurons made of LUTs, synapses made of routing: now you know which slab of that fabric to buy.