The state of open FPGA IP

A live snapshot of the LibFPGA registry: how much open FPGA IP we track, how much of it our open toolchain has actually verified, and what it is made of. Badges are earned, never self-declared.

Cores tracked
84
Verified
19 (23%)
Categories
20
Languages
9

Verification badges earned by the toolchain: lint 19 · synthesis 19 · testbench 3 · formal 1. Each is proven by actually running the check, see any core page for the evidence.

By category

CPU 15
maths 7
memory 7
retro computing 6
video 6
accelerator 5
audio 4
interconnect 4
SoC 4
USB 4
crypto 3
debug 3
DSP 3
networking 3
automotive 2
camera 2
library 2
sensor 2
example 1
motor control 1

By language

verilog 48
systemverilog 15
vhdl 8
python 7
chisel 5
migen 4
amaranth 2
myhdl 1
spinalhdl 1

By license

GPL-3.0 16
MIT 16
Apache-2.0 14
BSD-2-Clause 8
BSD-3-Clause 8
LGPL-3.0 4
Solderpad-0.51 4
Unspecified 3
CERN-OHL-W-2.0 2
GPL-2.0 2
ISC 2
LGPL-2.1 2
BSD-style 1
NVDLA Open License 1
See repository 1

By maturity

stable 61
production 14
beta 8
experimental 1

Most verified cores

The registry's own ranking: earned verification first, then maturity. Browse the full registry →

  • 1 libfpga Featured stable Verified reusable Verilog building blocks for FPGA designs. verilog MIT ✓ verified 4 checks
  • 2 fpga-neuron stable An educational neural network on an FPGA, from a single neuron to an XOR net. verilog MIT ✓ verified 3 checks
  • 3 libfpga-myhdl beta The same building blocks in MyHDL, hardware described in Python. myhdlpython MIT ✓ verified 3 checks
  • 4 core_jpeg stable A high-throughput JPEG decoder in Verilog. verilog Apache-2.0 ✓ verified 2 checks
  • 5 core_sdram_axi4 stable An SDRAM controller with a standard AXI4 interface. verilog GPL-3.0 ✓ verified 2 checks
  • 6 FPGA-DDR-SDRAM stable A DDR1 controller that gives low-end FPGAs cheap, large memory. verilog GPL-3.0 ✓ verified 2 checks
  • 7 FPGA-SDcard-Reader stable An FPGA SD-card reader with a FAT file-system layer. verilog GPL-3.0 ✓ verified 2 checks
  • 8 FPGA-USB-Device stable An FPGA-based USB 1.1 full-speed device (no PHY chip). verilog LGPL-2.1 ✓ verified 2 checks

    • Resource cost, measured

    LUT4 and flip-flop counts our synthesis run reported for verified cores (a technology-neutral yosys estimate).

    CoreLUT4sFlip-flops
    core_jpeg 43,386 30,236
    FPGA-DDR-SDRAM 16,350 17,634
    secworks/aes 10,030 2,994
    PDM Microphone Interface 9,832 2,877
    sdspi 8,426 9,008
    FPGA-SDcard-Reader 7,680 1,168
    secworks/chacha 6,504 1,940
    wb2axip 5,866 2,244