Frequency dividers: how to make a slower clock (and when not to)

Almost every FPGA design needs more than one rate. The board gives you a 100 MHz crystal, but your UART wants 115200 baud, your SPI display wants 25 MHz, your heartbeat LED wants about 1 Hz, and your debounce logic wants a tick every millisecond. A frequency divider is the small piece of logic that turns one fast clock into these slower rates. It is one of the first things you build, and, as we will see, one of the first things people build wrong.

Let's start from a single flip-flop and work up to an arbitrary divide-by-N, run one in the browser, and then cover the part every course skips: when you should not make a "clock" at all.

Divide by two: one flip-flop

The whole idea rests on a single flip-flop wired to toggle. Feed a D flip-flop's inverted output back to its own input, and on every rising clock edge it flips. Two input cycles make one output cycle, so the output is exactly half the frequency, with a perfect 50% duty cycle for free:

D Q Q' clk out = clk ÷ 2 Q' fed back to D: the flip-flop toggles

That 50% duty cycle matters: a divided clock made by counting (below) is often not 50/50, and a lopsided clock is a real problem for anything that uses both edges.

Divide by 2, 4, 8, …: a binary counter

Chain the idea, or, better on an FPGA, just build a binary counter and read off its bits. Bit 0 flips every clock, bit 1 every two, bit 2 every four. Each higher bit is the clock divided by the next power of two:

clk ÷2 ÷4 ÷8 
reg [2:0] count = 0;
always @(posedge clk) count <= count + 1'b1;

wire clk_div2 = count[0];   // clk / 2
wire clk_div4 = count[1];   // clk / 4
wire clk_div8 = count[2];   // clk / 8

Use a synchronous counter like this, not a ripple counter where each flip-flop clocks the next. Ripple dividers look tidy in a textbook but each stage adds delay, so the taps drift apart and skew piles up. A single counter clocked by one clock keeps every bit aligned.

Divide by any N

Powers of two are the easy case. For an arbitrary ratio you count input cycles and fold the counter back to zero at N, producing an output that is high for the first half of each period. Even N gives an exact 50% duty cycle; odd N lands one cycle off. Here it is, running for real: press Run, then change DIV and watch the output period stretch or shrink while the fast input clock stays the same.

The full project (fork it, grab the VCD, try DIV = 5 to see the odd-N wobble) is in the gallery. Want a target frequency worked out for you, counter width and all? The clock divider calculator does the arithmetic.

A clean 50% for odd N

If you need a true 50% duty from an odd divisor, one counter can't do it, half a cycle is only reachable between clock edges. The classic trick runs two dividers, one on the rising edge and one on the falling edge, and ORs them, so the output can change on both edges and split an odd count evenly. It costs a second small counter and is worth it only when the duty cycle really must be 50/50.

The part courses skip: don't clock with it

Here is the mistake almost everyone makes first. You build a divide-by-N, get a nice slow clk_div net, and wire it straight into the clock input of the logic you want to run slowly. It simulates perfectly. On hardware it is a latent bug.

✗ clk → ÷N → used as a clock clk ÷ N regs the divided net has no clock tree: skew and hold-time bugs ✓ clk → clock everywhere, ÷N → enable clk regs ÷ N en every register on the real clock; the strobe gates updates

An FPGA has a few dedicated clock trees: low-skew networks that fan a clock out to thousands of flip-flops so they all tick together. A clock you cook up in the fabric does not ride one. It arrives at different flip-flops at noticeably different times, the timing tools can't analyze it properly, and you get intermittent hold-time failures, the kind that pass on your bench and fail on someone else's board.

The fix is almost always one of two things:

reg [$clog2(DIV)-1:0] cnt = 0;
wire tick = (cnt == DIV-1);      // one-cycle strobe at clk / DIV
always @(posedge clk) cnt <= tick ? 0 : cnt + 1'b1;

always @(posedge clk)
    if (tick) begin
        // ... runs once every DIV cycles, still on `clk`
    end

Divide in logic for enables; use a PLL for clocks. And if you do end up with two real clocks, remember that any signal passing between them is now a clock domain crossing and needs a synchronizer.

Where dividers show up

Once you have a solid divider (or strobe generator), it is everywhere:

Try it, then dig in

Change DIV in the divider above and watch a fast clock become a slow one, then build the enable-based version for real hardware. More to read:

rtlclockstiming

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