Asynchronous FIFO

Move a data stream safely between two independent clocks.

When to use it

When a stream has to cross from one clock domain to another, a plain register won't do: a multi-bit value sampled mid-change can be garbage. A dual-clock FIFO is the standard answer, the writer pushes on its clock, the reader pops on theirs, and the FIFO handles the crossing.

How it works

Two pointers walk a shared memory, one per clock. The clever part is that each pointer is passed to the other domain as Gray code, so the synchronized value is only ever off by one step, never a corrupt in-between. wfull and rempty are registered comparisons of the local pointer against the synchronized remote one. (This is the classic Cummings design.)

Gotchas

Try it

Runs on our simulator, edit the code and press Run to see the waveform.

Open & fork in the playground → Ship the verified version: lfpga add lfpga_fifo_async

The runnable example above is a teaching version. The libfpga library ships a hardened, parameterised, CI-tested module (lfpga_fifo_async) for production use.

Next recipe: Skid buffer