Synchronous FIFO

Buffer a stream between a producer and a consumer on one clock.

When to use it

A FIFO (first-in, first-out queue) decouples a producer from a consumer: write when there's room, read when there's data, and the two don't have to move in lockstep. This one is synchronous, both sides share a clock. For crossing clock domains you need an async FIFO with gray-coded pointers instead.

How it works

A small memory plus a write pointer and a read pointer. The trick for telling full from empty, both are "pointers equal", is to make each pointer one bit wider than the address: when the extra bits differ but the address bits match, the FIFO is full.

Gotchas

Try it

Runs on our simulator, edit the code and press Run to see the waveform.

Open & fork in the playground → Ship the verified version: lfpga add lfpga_fifo_sync

The runnable example above is a teaching version. The libfpga library ships a hardened, parameterised, CI-tested module (lfpga_fifo_sync) for production use.

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