PWM Calculator
For a counter-based PWM on a given clock, find the PWM frequency, the number of duty-cycle steps, the resolution in bits and percent, and the smallest pulse. See the frequency-versus-resolution trade-off across counter widths, and get a ready-to-use parameterised Verilog module.
Results
- PWM frequency
- 390.6 kHz
- PWM period
- 2.56 us
- Duty steps
- 256 (0 to 255)
- Duty resolution
- 0.3906% per step
- Smallest pulse
- 10 ns (one clock)
Frequency vs resolution @ 100 MHz
| Bits | Steps | Res | PWM freq | Notes |
|---|---|---|---|---|
| 4 | 16 | 6.25% | 6.25 MHz | smooth |
| 5 | 32 | 3.12% | 3.125 MHz | smooth |
| 6 | 64 | 1.56% | 1.562 MHz | smooth |
| 7 | 128 | 0.781% | 781.2 kHz | smooth |
| 8 | 256 | 0.391% | 390.6 kHz | smooth |
| 9 | 512 | 0.195% | 195.3 kHz | smooth |
| 10 | 1024 | 0.0977% | 97.66 kHz | smooth |
| 11 | 2048 | 0.0488% | 48.83 kHz | smooth |
| 12 | 4096 | 0.0244% | 24.41 kHz | smooth |
| 13 | 8192 | 0.0122% | 12.21 kHz | smooth |
| 14 | 16384 | 0.0061% | 6.104 kHz | smooth |
| 15 | 32768 | 0.00305% | 3.052 kHz | smooth |
| 16 | 65536 | 0.00153% | 1.526 kHz | smooth |
Notes
- PWM frequency = clock / 2^bits. Each extra bit of duty resolution halves the frequency, so raise the clock if you need both.
- Keep the PWM frequency above ~1 kHz for flicker-free LED dimming, and well above the audible band (>20 kHz) for motors to run quietly.
- For a fixed target frequency, a fractional accumulator (see the clock divider) hits it more precisely than a power-of-two counter.
// Counter-based PWM, 8-bit duty. out is high while cnt < duty.
// Generated by libfpga.com/tools/pwm-calculator
module pwm #(parameter W = 8) (
input wire clk,
input wire [W-1:0] duty, // 0 = always off, 2^W-1 = (almost) always on
output wire out
);
reg [W-1:0] cnt = 0;
always @(posedge clk) cnt <= cnt + 1'b1;
assign out = (cnt < duty);
endmoduleAbout this tool
A counter-based PWM ramps a counter 0 to 2^N-1 and drives the output high while the counter is below the duty value. One full ramp is one PWM period, so the PWM frequency is clock / 2^N: every bit of duty resolution you add halves the PWM frequency. That's the fundamental trade-off, fine dimming steps or a high, flicker-free frequency, pick two and you can't have the third without a faster clock. This finds the numbers and generates the module; the PWM recipe explains the idea.