Open-source FPGA interconnect cores

Open bus and interconnect IP for FPGAs: AXI and AXI-Lite crossbars, Wishbone bridges and adapters. 4 curated cores, ranked by earned verification. Add one to your project in one command with lfpga, or browse the whole registry.

  1. 1 verilog-axi stable A comprehensive set of AXI4 infrastructure components for FPGAs. verilog MIT ✓ verified 2 checks
  2. 2 verilog-uart stable A simple, widely-used Verilog UART with an AXI-Stream interface. verilog MIT ✓ verified 2 checks
  3. 3 wb2axip stable Formally verified Wishbone and AXI bus bridges and utilities. verilog Apache-2.0 ✓ verified 2 checks
  4. 4 verilog-pcie stable PCI Express interface components for FPGAs, in Verilog. verilog MIT ★ 1,619 pending

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