PACoGen
betaPosit arithmetic core generator: parameterized Verilog adder, multiplier, divider.
Install with
lfpga
lfpga add pacogen
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[](https://libfpga.com/cores/pacogen)
- 81 GitHub stars
About
An open-source parameterized Verilog generator for posit (Unum Type III) arithmetic, producing adders, multipliers and dividers for any word size and exponent size with correct rounding. It is backed by the well cited PACoGen paper (Jaiswal and So, IEEE Access 2019).