Metastable

Sample the flip-flop while the clock edge is inside the green data-valid window. Every capture speeds the clock up and shrinks the window, until you are forced into the yellow setup/hold danger zone, where the output goes metastable and resolves at random. You cannot win forever. That is the whole point. How many can you capture before the chip gets you?

What you're actually learning

When a signal changes too close to a clock edge, violating the flip-flop's setup or hold time, the output can hang between 0 and 1 before settling to a random value. That is metastability, and it is exactly why moving a signal from one clock domain to another safely needs a two-flip-flop synchronizer: the first stage may go metastable, and you give it a full clock cycle to settle before anything downstream looks at it. In this game there is no synchronizer to save you, so the odds catch up eventually. In real hardware, that is a bug you design out, not a score you chase.

Enjoyed that? Try Logic Golf: Beat the Synthesizer, or learn the real thing in the hands-on course.