Setup & Hold Time

The keep-out window around a clock edge.

A flip-flop needs its input stable for a small window around the clock edge: setup time before the edge, hold time after it. Data arriving too late (setup violation) or changing too soon after (hold violation) risks metastability or wrong capture.

Setup violations are fixed by slowing the clock or shortening the path — they set Fmax. Hold violations are clock-skew problems the router fixes with deliberate delay, and a post-route hold violation is a build-killer, not a slow-down. Static timing analysis checks every path against both, which is why synchronous design scales.