Metastability

When a flip-flop can't decide.

Violate a flip-flop's setup or hold window and its output can hover between 0 and 1 for an unbounded time before randomly resolving — that's metastability. It can't be prevented when sampling truly asynchronous signals; it can only be given time to resolve.

The standard cure is the two-flop synchronizer: the first flop may go metastable, the second samples it a full cycle later, by which time the probability of still-undecided is astronomically small (MTBF measured in years). The CDC generator produces properly attributed synchronizers, and every CDC structure is built on this idea.

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Bitstream · Block RAM (BRAM) · Clock Domain Crossing (CDC) · Constraint · DSP Slice · Flip-Flop · Fmax · HLS (High-Level Synthesis) · LUT (Lookup Table) · Place & Route · PLL / MMCM · Setup & Hold Time · Soft-Core CPU · Synthesis · Testbench · Timing Closure · Transceiver (SerDes)