UART receiver

Recover a byte from a serial line with no shared clock.

When to use it

The other half of a UART link: turn the incoming rx wire back into bytes. There's no clock to sample on, so the receiver has to find the start bit itself and then sample each data bit at its centre, timing everything from its own clock.

How it works

The line idles high. A falling edge means a start bit, so wait half a bit to land in the middle of it, confirm it's still low, then sample every CLKS_PER_BIT clocks for the 8 data bits (LSB first). After the stop bit, pulse valid for one clock with the byte in data. The raw rx pin is synchronized through two flops first, it's asynchronous to this clock.

Gotchas

Try it

Runs on our simulator, edit the code and press Run to see the waveform.

Open & fork in the playground → Ship the verified version: lfpga add lfpga_uart_rx

The runnable example above is a teaching version. The libfpga library ships a hardened, parameterised, CI-tested module (lfpga_uart_rx) for production use.

Next recipe: Asynchronous FIFO