Verilog schematic viewer
Paste Verilog and see the RTL schematic Yosys infers from it, muxes, adders, and flip-flops drawn as a diagram you can pan and zoom. A fast way to check that your code elaborates into the hardware you meant.
About this tool
The schematic comes from Yosys, the open-source synthesis tool: your Verilog is elaborated to an RTL netlist (word-level muxes, arithmetic and registers), then drawn with cell captions. It is the fastest way to answer "did my code build the circuit I intended?", a stray latch, an accidental priority mux, or a wider adder than you expected all jump out visually. Want to see it run too? The playground simulates the same design and shows the waveform, and also has this schematic view built in.