The LibFPGA blog
Practical FPGA design, one problem at a time: FIFOs and clock domains, timing closure, RISC-V soft cores, and the tools that make the hard parts routine.
Ring oscillators on FPGAs: free clocks, true randomness, and a security foot-gun
A ring oscillator is the simplest circuit that refuses to sit still. Wire an odd number of inverters into a loop and there is no set of logic levels that keeps every gate happy: whatever value you pick, it propagates around the ring, comes back inverted, and forces the first gate to flip. The nodes chase each other around forever, and the loop oscillates all by itself, with no crystal, no clock input, nothing but gates and the time it takes a signal to travel through them.
Frequency dividers: how to make a slower clock (and when not to)
Almost every FPGA design needs more than one rate. The board gives you a 100 MHz crystal, but your UART wants 115200 baud, your SPI display wants 25 MHz, your heartbeat LED wants about 1 Hz, and your debounce logic wants a tick every millisecond. A frequency divider is the small piece of logic that turns one fast clock into these slower rates. It is one of the first things you build, and, as we will see, one of the first things people build wrong.
FPGA vs CPU vs GPU: three ways to compute
Every digital problem can run on a CPU, a GPU, or an FPGA, but the three chips go about it in completely different ways, and the differences are easiest to see if you just look at the silicon. A useful cartoon: a CPU is a few big, chunky blocks, a GPU is thousands of thin, long rectangles, and an FPGA is a sea of tiny blocks with wires running between all of them.
How to pick a RISC-V soft core for your FPGA
"RISC-V" is not a processor, it is an instruction set, and that is the good news: dozens of open, free, silicon-proven cores speak it, from ones that tuck into a corner of the smallest FPGA to ones that boot Linux. The catch is that "just drop in a RISC-V core" hides a real decision. Pick the wrong one and you either burn three quarters of your fabric on a CPU you did not need, or you discover halfway through that your core cannot do the one thing the project required. Here is how to choose on purpose.
How to cross a clock domain without corrupting your data
Every non-trivial FPGA design ends up with more than one clock: a 100 MHz core and a 125 MHz Ethernet MAC, a fast datapath and a slow control bus, an ADC clock and everything else. The moment a signal made in one clock domain is read in another you have a clock domain crossing (CDC), and if you wire it up naively it will work in simulation, pass on the bench, and then fail in the field one time in ten thousand. Here is why, and here is the small set of patterns that make it safe.
Introducing lfpga: a package manager for FPGA development
Every other corner of software has a package manager. Python has pip, Rust
You don't need a board to start FPGA design
The most common question from people getting into FPGAs is "which board
The neural micro-kit: turning a trained network into verified hardware
We've written twice about neural networks and FPGAs. First the idea:
MyHDL: describe hardware in Python (and try it in your browser now)
Verilog and VHDL are the languages of FPGA design, and they're worth
libfpga v0.1.0: a standard library for FPGAs, verified in public
Every FPGA team maintains a private folder of "the good blocks", the
How many bits do you actually need? Precision as a design knob
Software gives you a fixed menu of number formats: float, double, maybe
Datacenters in space: how FPGAs compute through a particle storm
The idea sounded like science fiction five years ago; now it has funding
"Why did I infer a latch?" · the warning, the cause, the two-line fix
It's the most-Googled synthesis warning in FPGA design:
The timing-closure triage checklist: what to do when slack goes negative
The timing report says -0.42 ns and the demo is Friday. Timing closure
Hello, LibFPGA: free tools that make FPGA design flow
Every FPGA project runs on the same small calculations. How deep does this
Your register map should be generated, not maintained
Every FPGA IP block carries the same three artifacts: the RTL that
FPGAs in high-frequency trading: the anatomy of a nanosecond
High-frequency trading is the one industry where FPGAs aren't the
FPGAs for AI: the chip that's already shaped like a neural network
Look at a neural network diagram and an FPGA die side by side, and the
FPGA vs microcontroller: how to actually choose
It's the most common question from newcomers and the most practical
FPGA reset strategies: async assert, sync deassert, and when to skip reset entirely
Reset looks like the simplest signal in a design and behaves like one of
Block RAM vs distributed RAM: where your memory actually goes
Write reg [7:0] mem [0:255]; and the synthesizer has a choice to make:
How to size an async FIFO (and why "double it" isn't a strategy)
The most common FIFO sizing method in industry is: take a guess, double it,