secworks/aes
stableA clean Verilog AES block cipher (128/256-bit).
Install with
lfpga
lfpga add secworks-aes
Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.
Verification
Signals earned by running the open toolchain against the public source. This listing is not yet owner-claimed; the badges reflect our build, not a maintainer's declaration. This is the registry's whole point: know it works before you clone it.
✓ Lints clean
Testbench passes
✓ Synthesizes
Formally proven
Converts to RTL
Last checked 2026-07-05 by the LibFPGA toolchain.
[](https://libfpga.com/cores/secworks-aes)
- 10030 LUT4s
- 452 GitHub stars
About
A readable, well-tested Verilog implementation of the AES block cipher (128 and 256-bit keys) per NIST FIPS 197, from the prolific secworks crypto-core collection. A solid drop-in when you need symmetric encryption in hardware and want a core you can actually audit.