FPGA core registry

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A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.

84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.

New: install any core with lfpga, the FPGA package manager. pip install lfpga, then lfpga add <name> to fetch verified sources into your build.

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Popular: risc-vcpumathsretrorv32chiselsecurityvideowishboneaudiocdcconsoledebugdspgeneratormac

5 of 84 cores

secworks/aes

stable

A clean Verilog AES block cipher (128/256-bit).

verilog BSD-2-Clause
✓ Lints clean ✓ Synthesizes

secworks/chacha

stable

A hardware implementation of the ChaCha stream cipher.

verilog BSD-2-Clause
✓ Lints clean ✓ Synthesizes

secworks/sha256

stable

A hardware implementation of the SHA-256 hash function.

verilog BSD-2-Clause
✓ Lints clean ✓ Synthesizes

Ibex

production

A small, production 32-bit RISC-V core with serious verification behind it.

systemverilog Apache-2.0
★ 1,944 verification pending

OpenTitan

beta

An open-source silicon root of trust (secure element).

systemverilog Apache-2.0
★ 3,507 verification pending