Fmax

The fastest clock your design can close timing at.

Fmax is the maximum clock frequency at which every register-to-register path still meets setup timing: the longest path's logic + routing delay determines the whole domain's speed limit. Tools report it after place and route; if Fmax is below your target clock, you have negative slack and a timing-closure task.

Raising Fmax means shortening the critical path: pipeline it (add flip-flops), reduce logic levels, or help the placer. Speed grades matter too — the same RTL closes at different Fmax on a -1 vs -3 part (see the part-number decoder).

More terms

Bitstream · Block RAM (BRAM) · Clock Domain Crossing (CDC) · Constraint · DSP Slice · Flip-Flop · HLS (High-Level Synthesis) · LUT (Lookup Table) · Metastability · Place & Route · PLL / MMCM · Setup & Hold Time · Soft-Core CPU · Synthesis · Testbench · Timing Closure · Transceiver (SerDes)