Flip-Flop

One bit of memory, updated on a clock edge.

A D flip-flop samples its input on the rising (or falling) edge of a clock and holds that value until the next edge. It's the atom of synchronous design: every register, counter, pipeline stage and state machine is flip-flops plus logic. FPGAs pair one or two flip-flops with every LUT, so they're effectively free — use them liberally for pipelining.

The edge-triggered discipline is what makes timing analysis possible: signals only change at known instants, so the tools can check that every path settles in time (see setup and hold).

Its level-sensitive cousin, the latch, is transparent while its enable is high — usually an accident in FPGA design. The latches vs flip-flops lesson shows the difference on a live waveform.