PLL / MMCM

On-chip clock synthesis.

A phase-locked loop multiplies and divides an input clock to make new frequencies: f_out = f_in x M / (D x O), with the VCO in the middle constrained to a legal range. FPGAs ship several (AMD/Xilinx calls the big ones MMCMs); they also de-skew, phase-shift, and clean up jitter.

Use a PLL for real frequency synthesis, and clock enables for merely slow logic — dividing a clock with a counter creates an unnecessary CDC. The PLL calculator finds legal M/D/O settings; the clock-divider tool covers the counter case and when to prefer enables.