Place & Route

Deciding where logic lives and how wires run.

After synthesis, place-and-route (P&R, or "implementation") assigns every primitive to a physical site on the die and finds routing paths for every net — an enormous optimization problem solved under timing constraints. Placement quality largely determines Fmax: related logic placed far apart pays routing delay that no LUT optimization can recover.

P&R is why FPGA builds take minutes to hours, and why results vary between runs (seeds). When timing almost closes, floorplanning (constraining blocks to regions) or re-pipelining beats re-running and hoping.