DSP Slice

The hardened multiply-accumulate engine.

A DSP slice (DSP48 on AMD/Xilinx, variously named elsewhere) is a hardened arithmetic unit: typically an 18x25 or 18x19 multiplier, a wide accumulator, and pre-adders, running far faster than the same logic built from LUTs. Filters, FFTs, matrix math and neural-network inference are budgeted in DSP slices.

Write a * b in RTL and synthesis maps it to DSP slices automatically (the multipliers lesson shows this). Peak arithmetic throughput ≈ DSP count x 2 ops x clock — the back-of-envelope in our FPGAs for AI article.