HLS (High-Level Synthesis)

C/C++ in, RTL out.

High-level synthesis compiles C/C++/SystemC (or Python via frameworks) into RTL: loops become pipelines, arrays become BRAMs, and pragmas steer parallelism. Vitis HLS and Intel's oneAPI flows are the mainstream tools; hls4ml rides HLS to put neural networks in physics triggers (see FPGAs for AI).

HLS shines for dataflow math — filters, codecs, matrix kernels — where its what-if exploration beats hand-written RTL for productivity. Control logic, interfaces and anything cycle-exact usually stay hand-written. Verify the output like any RTL: in simulation, with a testbench.

More terms

Bitstream · Block RAM (BRAM) · Clock Domain Crossing (CDC) · Constraint · DSP Slice · Flip-Flop · Fmax · LUT (Lookup Table) · Metastability · Place & Route · PLL / MMCM · Setup & Hold Time · Soft-Core CPU · Synthesis · Testbench · Timing Closure · Transceiver (SerDes)