Testbench

The code that tests your code.

A testbench is a non-synthesizable HDL module that instantiates your design, drives its inputs, and checks its outputs in simulation. It's where initial blocks, delays (#10), file I/O and $display are legal — none of which belong in shippable RTL.

Minimum viable testbench: generate a clock, apply a reset, wiggle inputs, dump a waveform ($dumpfile/$dumpvars), and $finish. Every lesson in our course ships one you can run and modify in the playground. The step up from eyeballing waveforms is self-checking testbenches: assert expected values and count errors — the pattern our register-map generator's own verification uses.