Constraint

Telling the tools your design's physical truth.

Constraints declare what the tools can't infer: which pins signals use, how fast clocks run, which paths are asynchronous or multi-cycle. They live in XDC files (Vivado) or SDC (Quartus), and they're as much part of the design as the RTL, an unconstrained clock isn't checked at all.

The two mandatory ones: create_clock for every clock pin, and pin placement/I/O standards for every port (the pinout converter generates the latter from a spreadsheet). Everything else, false paths, max delays, CDC exceptions, exists to make the timing report match reality.