FPGA core registry

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A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.

84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.

New: install any core with lfpga, the FPGA package manager. pip install lfpga, then lfpga add <name> to fetch verified sources into your build.

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Popular: risc-vcpumathsretrorv32chiselsecurityvideowishboneaudiocdcconsoledebugdspgeneratormac

7 of 84 cores

core_jpeg

stable

A high-throughput JPEG decoder in Verilog.

verilog Apache-2.0
✓ Lints clean ✓ Synthesizes

FPGA DisplayPort

stable

A from-scratch DisplayPort implementation for FPGAs.

vhdl MIT
★ 311 verification pending

FPGA-JPEG-LS-encoder

stable

A lossless JPEG-LS image encoder in Verilog.

verilog GPL-3.0
★ 331 verification pending

hdl-util/hdmi

stable

Send true HDMI video and audio from an FPGA, no IP licence.

systemverilog MIT
★ 1,280 verification pending

hdl-util/mipi-csi-2

stable

Capture MIPI CSI-2 video from a Raspberry Pi Camera on an FPGA.

systemverilog MIT
★ 76 verification pending

Project F

stable

Exciting open-source FPGA graphics and video designs to build on.

systemverilog MIT
★ 781 verification pending

vgasim

stable

A video display simulator with real VGA/HDMI generation cores.

verilog GPL-3.0
★ 182 verification pending