A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.
84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.
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Popular: risc-vcpumathsretrorv32chiselsecurityvideowishboneaudiocdcconsoledebugdspgeneratormac
18 of 84 cores
CV32E40P
productionAn industrial-grade 32-bit RISC-V embedded core from OpenHW.
CVA6 (Ariane)
productionA 6-stage 64-bit RISC-V core that boots Linux.
CVFPU (FPnew)
productionA parametric floating-point unit for RISC-V and transprecision.
Hazard3
productionThe 3-stage RISC-V core inside the RP2350.
Ibex
productionA small, production 32-bit RISC-V core with serious verification behind it.
PicoRV32
productionA size-optimized RISC-V CPU that fits in a corner of your FPGA.
riscv-dbg
productionThe standard open RISC-V debug module and JTAG transport.
Rocket Chip
productionThe Chisel generator behind a whole family of RISC-V SoCs.
VexRiscv
productionAn FPGA-friendly, highly configurable 32-bit RISC-V, built in SpinalHDL.
Ara
stableA 64-bit RISC-V Vector (RVV) unit from PULP.
biRISC-V
stableA 32-bit superscalar, dual-issue RISC-V CPU.
NEORV32
stableA customizable MCU-class RISC-V SoC in platform-independent VHDL.
Saturn
stableA Chisel implementation of the ratified RISC-V Vector 1.0 spec.
SERV
stableThe award-winning bit-serial RISC-V: the world's smallest.
SonicBOOM (riscv-boom)
stableThe Berkeley out-of-order RISC-V machine.
ultraembedded/riscv
stableA compact RV32IM RISC-V CPU core in Verilog.
VeeR EH1
stableA dual-issue, in-order RISC-V core (formerly SweRV).
DarkRISCV
betaA minimal RISC-V core written from scratch in one night.
No cores match those filters. Clear.