FPGA core registry

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A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.

84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.

New: install any core with lfpga, the FPGA package manager. pip install lfpga, then lfpga add <name> to fetch verified sources into your build.

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Popular: risc-vcpumathsretrorv32chiselsecurityvideowishboneaudiocdcconsoledebugdspgeneratormac

6 of 84 cores

fpga-neuron

stable

An educational neural network on an FPGA, from a single neuron to an XOR net.

verilog MIT
✓ Lints clean ✓ Testbench passes ✓ Synthesizes

libfpga-myhdl

beta

The same building blocks in MyHDL, hardware described in Python.

myhdlpython MIT
✓ Lints clean ✓ Testbench passes ✓ Synthesizes

verilog-ethernet

stable

Ethernet MAC and UDP/IP stack components in Verilog.

verilog MIT
✓ Lints clean ✓ Synthesizes

LiteEth

stable

A small-footprint, configurable Ethernet core.

migenpython BSD-2-Clause
★ 286 verification pending

machdyne/fpga-dac

stable

A sigma-delta audio DAC and PCM player core.

verilog BSD-style
★ 6 verification pending

SonicBOOM (riscv-boom)

stable

The Berkeley out-of-order RISC-V machine.

chisel BSD-3-Clause
★ 2,195 verification pending