Open-source FPGA CPU cores

Open-source soft processor cores for FPGAs, from tiny RISC-V microcontrollers to Linux-capable application cores. 15 curated cores, ranked by earned verification. Add one to your project in one command with lfpga, or browse the whole registry.

  1. 1 CV32E40P production An industrial-grade 32-bit RISC-V embedded core from OpenHW. systemverilog Solderpad-0.51 ★ 1,258 pending
  2. 2 CVA6 (Ariane) production A 6-stage 64-bit RISC-V core that boots Linux. systemverilog Solderpad-0.51 ★ 2,995 pending
  3. 3 Hazard3 production The 3-stage RISC-V core inside the RP2350. verilog Apache-2.0 ★ 1,065 pending
  4. 4 Ibex production A small, production 32-bit RISC-V core with serious verification behind it. systemverilog Apache-2.0 ★ 1,944 pending
  5. 5 PicoRV32 production A size-optimized RISC-V CPU that fits in a corner of your FPGA. verilog ISC ★ 4,244 pending
  6. 6 Rocket Chip production The Chisel generator behind a whole family of RISC-V SoCs. chisel Apache-2.0 ★ 3,807 pending
  7. 7 VexRiscv production An FPGA-friendly, highly configurable 32-bit RISC-V, built in SpinalHDL. spinalhdl MIT ★ 3,181 pending
  8. 8 biRISC-V stable A 32-bit superscalar, dual-issue RISC-V CPU. verilog Apache-2.0 ★ 1,273 pending
  9. 9 mor1kx stable An OpenRISC 1000 processor core. verilog CERN-OHL-W-2.0 ★ 586 pending
  10. 10 SERV stable The award-winning bit-serial RISC-V: the world's smallest. verilog ISC ★ 1,826 pending
  11. 11 SonicBOOM (riscv-boom) stable The Berkeley out-of-order RISC-V machine. chisel BSD-3-Clause ★ 2,195 pending
  12. 12 ultraembedded/riscv stable A compact RV32IM RISC-V CPU core in Verilog. verilog BSD-3-Clause ★ 1,748 pending
  13. 13 VeeR EH1 stable A dual-issue, in-order RISC-V core (formerly SweRV). systemverilog Apache-2.0 ★ 952 pending
  14. 14 ZipCPU stable A small, light, pipelined RISC soft-core with a rigorous pedigree. verilog GPL-3.0 ★ 1,558 pending
  15. 15 DarkRISCV beta A minimal RISC-V core written from scratch in one night. verilog BSD-3-Clause ★ 2,581 pending

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