FPGA core registry

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A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.

84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.

New: install any core with lfpga, the FPGA package manager. pip install lfpga, then lfpga add <name> to fetch verified sources into your build.

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Popular: risc-vcpumathsretrorv32chiselsecurityvideowishboneaudiocdcconsoledebugdspgeneratormac

4 of 84 cores

libfpga

Featured stable

Verified reusable Verilog building blocks for FPGA designs.

verilog MIT
✓ Lints clean ✓ Testbench passes ✓ Synthesizes ✓ Formally proven

libfpga-myhdl

beta

The same building blocks in MyHDL, hardware described in Python.

myhdlpython MIT
✓ Lints clean ✓ Testbench passes ✓ Synthesizes

FPGA-USB-Device

stable

An FPGA-based USB 1.1 full-speed device (no PHY chip).

verilog LGPL-2.1
✓ Lints clean ✓ Synthesizes

core_usb_cdc

beta

A basic USB-CDC (serial) device core in Verilog.

verilog LGPL-2.1
✓ Lints clean ✓ Synthesizes