FPGA core registry

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A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.

84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.

Want our own building blocks? The libfpga library is a first-party, formally-verified collection listed right here in the registry. Prefer to learn a pattern hands-on first? Try the runnable recipes.

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Popular: risc-vcpumathsretrorv32chiselsecurityvideowishboneaudiocdcconsoledebugdspgeneratormac

5 of 84 cores

core_sdram_axi4

stable

An SDRAM controller with a standard AXI4 interface.

verilog GPL-3.0
✓ Lints clean ✓ Synthesizes

verilog-uart

stable

A simple, widely-used Verilog UART with an AXI-Stream interface.

verilog MIT
✓ Lints clean ✓ Synthesizes

PDM Microphone Interface

experimental

A PDM MEMS microphone interface (PDM to PCM) for FPGAs.

verilog See repository
✓ Lints clean ✓ Synthesizes

ADAT USB Audio Interface

stable

An FPGA-based USB 2.0 high-speed audio interface with ADAT.

amaranthpython CERN-OHL-W-2.0
★ 186 verification pending

verilog-pcie

stable

PCI Express interface components for FPGAs, in Verilog.

verilog MIT
★ 1,619 verification pending