FPGA core registry

Share your core Registry insights → For IP vendors →

A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.

84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.

Want our own building blocks? The libfpga library is a first-party, formally-verified collection listed right here in the registry. Prefer to learn a pattern hands-on first? Try the runnable recipes.

Browse by category

all 84 cpu 15maths 7memory 7retro 6video 6accelerator 5audio 4interconnect 4soc 4usb 4crypto 3debug 3dsp 3networking 3automotive 2camera 2library 2sensor 2example 1motor 1

All cores

clear

Popular: risc-vcpumathsretrorv32chiselsecurityvideowishboneaudiocdcconsoledebugdspgeneratormac

4 of 84 cores

core_sdram_axi4

stable

An SDRAM controller with a standard AXI4 interface.

verilog GPL-3.0
✓ Lints clean ✓ Synthesizes

FPGA-DDR-SDRAM

stable

A DDR1 controller that gives low-end FPGAs cheap, large memory.

verilog GPL-3.0
✓ Lints clean ✓ Synthesizes

LiteDRAM

stable

A small-footprint, configurable DRAM controller.

migenpython BSD-2-Clause
★ 521 verification pending

sdram-fpga

stable

A simple, readable SDRAM controller core in VHDL.

vhdl MIT
★ 126 verification pending