A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.
84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.
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Popular: risc-vcpumathsretrorv32chiselsecurityvideowishboneaudiocdcconsoledebugdspgeneratormac
4 of 84 cores
verilog-axi
stableA comprehensive set of AXI4 infrastructure components for FPGAs.
verilog-uart
stableA simple, widely-used Verilog UART with an AXI-Stream interface.
wb2axip
stableFormally verified Wishbone and AXI bus bridges and utilities.
verilog-pcie
stablePCI Express interface components for FPGAs, in Verilog.
No cores match those filters. Clear.