A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.
84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.
Want our own building blocks? The libfpga library is a first-party, formally-verified collection listed right here in the registry. Prefer to learn a pattern hands-on first? Try the runnable recipes.
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63 of 84 cores
libfpga
Featured stableVerified reusable Verilog building blocks for FPGA designs.
fpga-neuron
stableAn educational neural network on an FPGA, from a single neuron to an XOR net.
core_jpeg
stableA high-throughput JPEG decoder in Verilog.
core_sdram_axi4
stableAn SDRAM controller with a standard AXI4 interface.
FPGA-DDR-SDRAM
stableA DDR1 controller that gives low-end FPGAs cheap, large memory.
FPGA-SDcard-Reader
stableAn FPGA SD-card reader with a FAT file-system layer.
FPGA-USB-Device
stableAn FPGA-based USB 1.1 full-speed device (no PHY chip).
sdspi
stableAn SD-card controller supporting SPI, SDIO and eMMC.
secworks/aes
stableA clean Verilog AES block cipher (128/256-bit).
secworks/chacha
stableA hardware implementation of the ChaCha stream cipher.
secworks/sha256
stableA hardware implementation of the SHA-256 hash function.
verilog-axi
stableA comprehensive set of AXI4 infrastructure components for FPGAs.
verilog-ethernet
stableEthernet MAC and UDP/IP stack components in Verilog.
verilog-uart
stableA simple, widely-used Verilog UART with an AXI-Stream interface.
wb2axip
stableFormally verified Wishbone and AXI bus bridges and utilities.
core_usb_cdc
betaA basic USB-CDC (serial) device core in Verilog.
core_usb_host
betaA basic USB 1.1 host controller for small systems.
PDM Microphone Interface
experimentalA PDM MEMS microphone interface (PDM to PCM) for FPGAs.
CV32E40P
productionAn industrial-grade 32-bit RISC-V embedded core from OpenHW.
CVA6 (Ariane)
productionA 6-stage 64-bit RISC-V core that boots Linux.
CVFPU (FPnew)
productionA parametric floating-point unit for RISC-V and transprecision.
FX68K
productionA cycle-accurate Motorola 68000 CPU core.
Hazard3
productionThe 3-stage RISC-V core inside the RP2350.
Ibex
productionA small, production 32-bit RISC-V core with serious verification behind it.
NVDLA
productionNVIDIA's open Deep Learning Accelerator, in RTL.
PicoRV32
productionA size-optimized RISC-V CPU that fits in a corner of your FPGA.
riscv-dbg
productionThe standard open RISC-V debug module and JTAG transport.
Ara
stableA 64-bit RISC-V Vector (RVV) unit from PULP.
biRISC-V
stableA 32-bit superscalar, dual-issue RISC-V CPU.
Caravel
stableThe standard open-silicon SoC harness for chip tapeouts.
core_audio
stableAn audio controller: I2S, S/PDIF and DAC output.
Corundum
stableAn open-source FPGA-based NIC and platform for in-network compute.
dawsonjon/fpu
stableA synthesizable IEEE-754 floating-point unit.
dblclockfft
stableA configurable pipelined FFT core generator.
dspfilters
stableA collection of demonstration digital filters, done rigorously.
FPGA-CAN
stableA lightweight CAN 2.0 bus controller for FPGAs.
FPGA-FOC
stableFPGA Field-Oriented Control for driving BLDC / PMSM motors.
FPGA-JPEG-LS-encoder
stableA lossless JPEG-LS image encoder in Verilog.
Genesis (MiSTer)
stableA Sega Genesis / Mega Drive core for MiSTer.
hdl-util/hdmi
stableSend true HDMI video and audio from an FPGA, no IP licence.
hdl-util/mipi-csi-2
stableCapture MIPI CSI-2 video from a Raspberry Pi Camera on an FPGA.
JTCORES
stableJose Tejada's FPGA-accurate arcade sound and system cores.
machdyne/fpga-dac
stableA sigma-delta audio DAC and PCM player core.
mipi_csi_receiver_FPGA
stableA widely-used MIPI CSI-2 camera sensor receiver in Verilog.
mor1kx
stableAn OpenRISC 1000 processor core.
NES (MiSTer)
stableA Nintendo Entertainment System core for MiSTer.
Nyuzi Processor
stableAn open GPGPU architecture for graphics and parallel compute.
OpenLogicBit
stableOpen logic-analyzer gateware (SUMP-compatible).
Project F
stableExciting open-source FPGA graphics and video designs to build on.
qspiflash
stableWishbone-controlled SPI and QSPI flash controllers.
SERV
stableThe award-winning bit-serial RISC-V: the world's smallest.
Sigma-Delta ADC
stableAn analog-to-digital converter built in FPGA fabric.
ultraembedded/riscv
stableA compact RV32IM RISC-V CPU core in Verilog.
VeeR EH1
stableA dual-issue, in-order RISC-V core (formerly SweRV).
verilog-pcie
stablePCI Express interface components for FPGAs, in Verilog.
vgasim
stableA video display simulator with real VGA/HDMI generation cores.
ZipCPU
stableA small, light, pipelined RISC soft-core with a rigorous pedigree.
ZipCPU CORDIC Generator
stableConfigurable CORDIC core generator for sine, cosine and vector rotation.
DarkRISCV
betaA minimal RISC-V core written from scratch in one night.
OpenTitan
betaAn open-source silicon root of trust (secure element).
PACoGen
betaPosit arithmetic core generator: parameterized Verilog adder, multiplier, divider.
seldridge Verilog Blocks
betaReusable Verilog blocks including pipelined square root and integer divider.
SV_DSM_CORE
betaA synthesizable delta-sigma modulator IP core.
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