A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.
84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.
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Popular: risc-vcpumathsretrorv32chiselsecurityvideowishboneaudiocdcconsoledebugdspgeneratormac
6 of 84 cores
riscv-dbg
productionThe standard open RISC-V debug module and JTAG transport.
VexRiscv
productionAn FPGA-friendly, highly configurable 32-bit RISC-V, built in SpinalHDL.
SonicBOOM (riscv-boom)
stableThe Berkeley out-of-order RISC-V machine.
ultraembedded/riscv
stableA compact RV32IM RISC-V CPU core in Verilog.
DarkRISCV
betaA minimal RISC-V core written from scratch in one night.
OpenTitan
betaAn open-source silicon root of trust (secure element).
No cores match those filters. Clear.