FPGA core registry

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A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.

84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.

Want our own building blocks? The libfpga library is a first-party, formally-verified collection listed right here in the registry. Prefer to learn a pattern hands-on first? Try the runnable recipes.

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27 of 84 cores

libfpga

Featured stable

Verified reusable Verilog building blocks for FPGA designs.

verilog MIT
✓ Lints clean ✓ Testbench passes ✓ Synthesizes ✓ Formally proven

fpga-neuron

stable

An educational neural network on an FPGA, from a single neuron to an XOR net.

verilog MIT
✓ Lints clean ✓ Testbench passes ✓ Synthesizes

libfpga-myhdl

beta

The same building blocks in MyHDL, hardware described in Python.

myhdlpython MIT
✓ Lints clean ✓ Testbench passes ✓ Synthesizes

FPGA-DDR-SDRAM

stable

A DDR1 controller that gives low-end FPGAs cheap, large memory.

verilog GPL-3.0
✓ Lints clean ✓ Synthesizes

FPGA-SDcard-Reader

stable

An FPGA SD-card reader with a FAT file-system layer.

verilog GPL-3.0
✓ Lints clean ✓ Synthesizes

FPGA-USB-Device

stable

An FPGA-based USB 1.1 full-speed device (no PHY chip).

verilog LGPL-2.1
✓ Lints clean ✓ Synthesizes

verilog-axi

stable

A comprehensive set of AXI4 infrastructure components for FPGAs.

verilog MIT
✓ Lints clean ✓ Synthesizes

PDM Microphone Interface

experimental

A PDM MEMS microphone interface (PDM to PCM) for FPGAs.

verilog See repository
✓ Lints clean ✓ Synthesizes

PicoRV32

production

A size-optimized RISC-V CPU that fits in a corner of your FPGA.

verilog ISC
★ 4,244 verification pending

VexRiscv

production

An FPGA-friendly, highly configurable 32-bit RISC-V, built in SpinalHDL.

spinalhdl MIT
★ 3,181 verification pending

ADAT USB Audio Interface

stable

An FPGA-based USB 2.0 high-speed audio interface with ADAT.

amaranthpython CERN-OHL-W-2.0
★ 186 verification pending

Corundum

stable

An open-source FPGA-based NIC and platform for in-network compute.

verilog BSD-2-Clause
★ 2,384 verification pending

FPGA DisplayPort

stable

A from-scratch DisplayPort implementation for FPGAs.

vhdl MIT
★ 311 verification pending

FPGA-CAN

stable

A lightweight CAN 2.0 bus controller for FPGAs.

verilog GPL-3.0
★ 352 verification pending

FPGA-FOC

stable

FPGA Field-Oriented Control for driving BLDC / PMSM motors.

verilog GPL-3.0
★ 937 verification pending

FPGA-JPEG-LS-encoder

stable

A lossless JPEG-LS image encoder in Verilog.

verilog GPL-3.0
★ 331 verification pending

hdl-util/hdmi

stable

Send true HDMI video and audio from an FPGA, no IP licence.

systemverilog MIT
★ 1,280 verification pending

hdl-util/mipi-csi-2

stable

Capture MIPI CSI-2 video from a Raspberry Pi Camera on an FPGA.

systemverilog MIT
★ 76 verification pending

JTCORES

stable

Jose Tejada's FPGA-accurate arcade sound and system cores.

verilog GPL-3.0
★ 307 verification pending

LiteScope

stable

A small, configurable on-chip logic analyzer for FPGAs.

migenpython BSD-2-Clause
★ 205 verification pending

LiteX

stable

Build your hardware easily: a Python-based SoC builder.

pythonmigen BSD-2-Clause
★ 3,975 verification pending

machdyne/fpga-dac

stable

A sigma-delta audio DAC and PCM player core.

verilog BSD-style
★ 6 verification pending

mipi_csi_receiver_FPGA

stable

A widely-used MIPI CSI-2 camera sensor receiver in Verilog.

verilog Unspecified
★ 478 verification pending

Project F

stable

Exciting open-source FPGA graphics and video designs to build on.

systemverilog MIT
★ 781 verification pending

sdram-fpga

stable

A simple, readable SDRAM controller core in VHDL.

vhdl MIT
★ 126 verification pending

Sigma-Delta ADC

stable

An analog-to-digital converter built in FPGA fabric.

verilog Unspecified
★ 74 verification pending

verilog-pcie

stable

PCI Express interface components for FPGAs, in Verilog.

verilog MIT
★ 1,619 verification pending