FPGA core registry

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A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.

84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.

Want our own building blocks? The libfpga library is a first-party, formally-verified collection listed right here in the registry. Prefer to learn a pattern hands-on first? Try the runnable recipes.

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Popular: risc-vcpumathsretrorv32chiselsecurityvideowishboneaudiocdcconsoledebugdspgeneratormac

23 of 84 cores

FPGA-USB-Device

stable

An FPGA-based USB 1.1 full-speed device (no PHY chip).

verilog LGPL-2.1
✓ Lints clean ✓ Synthesizes

secworks/aes

stable

A clean Verilog AES block cipher (128/256-bit).

verilog BSD-2-Clause
✓ Lints clean ✓ Synthesizes

secworks/chacha

stable

A hardware implementation of the ChaCha stream cipher.

verilog BSD-2-Clause
✓ Lints clean ✓ Synthesizes

verilog-ethernet

stable

Ethernet MAC and UDP/IP stack components in Verilog.

verilog MIT
✓ Lints clean ✓ Synthesizes

verilog-uart

stable

A simple, widely-used Verilog UART with an AXI-Stream interface.

verilog MIT
✓ Lints clean ✓ Synthesizes

wb2axip

stable

Formally verified Wishbone and AXI bus bridges and utilities.

verilog Apache-2.0
✓ Lints clean ✓ Synthesizes

CTU CAN FD

production

An open, Linux-supported CAN FD controller IP core.

vhdl MIT
★ 63 verification pending

Rocket Chip

production

The Chisel generator behind a whole family of RISC-V SoCs.

chisel Apache-2.0
★ 3,807 verification pending

Caravel

stable

The standard open-silicon SoC harness for chip tapeouts.

verilog Apache-2.0
★ 400 verification pending

dblclockfft

stable

A configurable pipelined FFT core generator.

verilog LGPL-3.0
★ 262 verification pending

hdl-util/hdmi

stable

Send true HDMI video and audio from an FPGA, no IP licence.

systemverilog MIT
★ 1,280 verification pending

hdl-util/mipi-csi-2

stable

Capture MIPI CSI-2 video from a Raspberry Pi Camera on an FPGA.

systemverilog MIT
★ 76 verification pending

intfftk

stable

A fully pipelined integer radix-2 FFT / IFFT IP core.

vhdl GPL-3.0
★ 97 verification pending

JTCORES

stable

Jose Tejada's FPGA-accurate arcade sound and system cores.

verilog GPL-3.0
★ 307 verification pending

LiteScope

stable

A small, configurable on-chip logic analyzer for FPGAs.

migenpython BSD-2-Clause
★ 205 verification pending

mipi_csi_receiver_FPGA

stable

A widely-used MIPI CSI-2 camera sensor receiver in Verilog.

verilog Unspecified
★ 478 verification pending

NEORV32

stable

A customizable MCU-class RISC-V SoC in platform-independent VHDL.

vhdl BSD-3-Clause
★ 2,168 verification pending

PoC Library

stable

A VHDL IP library with arithmetic units: dividers, square root and prefix adders.

vhdl Apache-2.0
★ 83 verification pending

ZipCPU

stable

A small, light, pipelined RISC soft-core with a rigorous pedigree.

verilog GPL-3.0
★ 1,558 verification pending

ZipCPU CORDIC Generator

stable

Configurable CORDIC core generator for sine, cosine and vector rotation.

verilog LGPL-3.0
★ 125 verification pending

PACoGen

beta

Posit arithmetic core generator: parameterized Verilog adder, multiplier, divider.

verilog BSD-3-Clause
★ 81 verification pending

seldridge Verilog Blocks

beta

Reusable Verilog blocks including pipelined square root and integer divider.

verilog Apache-2.0
★ 626 verification pending

SV_DSM_CORE

beta

A synthesizable delta-sigma modulator IP core.

systemverilog MIT
★ 2 verification pending