A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.
84 curated open cores across 20 categories. Badges are earned only where LibFPGA has actually run the checks; the rest are marked verification pending. Own a listed repo? Claim it by manifest file or GitHub sign-in.
Want our own building blocks? The libfpga library is a first-party, formally-verified collection listed right here in the registry. Prefer to learn a pattern hands-on first? Try the runnable recipes.
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Popular: risc-vcpumathsretrorv32chiselsecurityvideowishboneaudiocdcconsoledebugdspgeneratormac
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libfpga
Featured stableVerified reusable Verilog building blocks for FPGA designs.
core_jpeg
stableA high-throughput JPEG decoder in Verilog.
core_sdram_axi4
stableAn SDRAM controller with a standard AXI4 interface.
FPGA-DDR-SDRAM
stableA DDR1 controller that gives low-end FPGAs cheap, large memory.
verilog-axi
stableA comprehensive set of AXI4 infrastructure components for FPGAs.
verilog-ethernet
stableEthernet MAC and UDP/IP stack components in Verilog.
verilog-uart
stableA simple, widely-used Verilog UART with an AXI-Stream interface.
wb2axip
stableFormally verified Wishbone and AXI bus bridges and utilities.
CTU CAN FD
productionAn open, Linux-supported CAN FD controller IP core.
CVA6 (Ariane)
productionA 6-stage 64-bit RISC-V core that boots Linux.
NVDLA
productionNVIDIA's open Deep Learning Accelerator, in RTL.
PicoRV32
productionA size-optimized RISC-V CPU that fits in a corner of your FPGA.
riscv-dbg
productionThe standard open RISC-V debug module and JTAG transport.
Rocket Chip
productionThe Chisel generator behind a whole family of RISC-V SoCs.
VexRiscv
productionAn FPGA-friendly, highly configurable 32-bit RISC-V, built in SpinalHDL.
Ara
stableA 64-bit RISC-V Vector (RVV) unit from PULP.
biRISC-V
stableA 32-bit superscalar, dual-issue RISC-V CPU.
Corundum
stableAn open-source FPGA-based NIC and platform for in-network compute.
FPGA-JPEG-LS-encoder
stableA lossless JPEG-LS image encoder in Verilog.
intfftk
stableA fully pipelined integer radix-2 FFT / IFFT IP core.
LiteDRAM
stableA small-footprint, configurable DRAM controller.
LiteEth
stableA small-footprint, configurable Ethernet core.
LiteX
stableBuild your hardware easily: a Python-based SoC builder.
NEORV32
stableA customizable MCU-class RISC-V SoC in platform-independent VHDL.
Nyuzi Processor
stableAn open GPGPU architecture for graphics and parallel compute.
ultraembedded/riscv
stableA compact RV32IM RISC-V CPU core in Verilog.
VeeR EH1
stableA dual-issue, in-order RISC-V core (formerly SweRV).
verilog-pcie
stablePCI Express interface components for FPGAs, in Verilog.
vgasim
stableA video display simulator with real VGA/HDMI generation cores.
ZipCPU
stableA small, light, pipelined RISC soft-core with a rigorous pedigree.
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